The Memory Hierarchy
This module builds on the foundation laid in previous modules on processor architecture and program optimization. It explores memory technologies, such as SRAM and DRAM, non-volatile storage, and the principles of memory hierarchy, including the locality principle and cache operation. The module delves into the design and implementation of caches, addressing direct-mapped and associative caches, block size, cache conflicts, and write strategies. This module is crucial for understanding how efficient memory usage can significantly impact system performance.
Topics Covered
- Technologies
- Locality
- Caches and Caching Strategies
- Writing cache-friendly Code
Learning Outcomes
After this week, you will be able to:
- Describe the different levels of the memory hierarchy and their characteristics.
- Analyze cache organization and mapping techniques (e.g., direct-mapped, set-associative, fully associative).
- Explain the principles of virtual memory and its role in address space management.
- Evaluate the trade-offs between memory hierarchy levels in terms of speed, capacity, and cost.
The content in this module is taken from MIT Open Courseware. Full video lectures of this material is available from https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c14/c14s2/.
Chris Terman. 6.004: Computation Structures. Spring 2017. Massachusetts Institute of Technology: MIT OpenCouseWare, https://ocw.mit.edu/. License: Creative Commons BY-NC-SA.